Performance Design Verification Engineer (Start ASAP)

Responsibilities

• Be part of a team to verify complex digital design blocks at the Subsystem level or Full Chip level by fully understanding the design specification and interacting with design engineers to identify key verification scenarios.

• Create and enhance constrained-random verification environments using UVM SystemVerilog or create complex multi-core-based C tests using reusable C test libs.

• Identify and write all types of coverage measures for stimulus and corner cases.

• Debug tests with design engineers to deliver functionally correct design blocks.

• Close coverage measures to identify verification holes and to show progress towards tape-out.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.

• Experience with performance verification and experience in gathering/interacting with Architecture and Modeling teams.

• Experience in C/C++ or System Verilog-based tests, test sequence development.

• Experience verifying digital logic at the RTL using SystemVerilog.

Preferred qualifications

• Experience in performance verification of complex Systems on-chip with multiple crossbars/Network on-chip.

• Experience with debugging performance and latency-related issues across multiple subsystems and Systems on-chip.

• Experience with Quality of Service, Real-time client Bandwidth, and other mechanisms of Bandwidth control.

• Knowledge of performance and latency architecture for an advanced RISC machine-based System-on-chip.

• Knowledge of performance measurement and debug in an emulation environment